1. Field of the Invention
The present invention generally relates to a semiconductor device. More particularly, the present invention relates to the structure of a protection circuit for protecting an input/output (I/O) circuit of a high frequency circuit processing a high frequency signal against breakdown due to electrostatic discharge.
2. Description of the Background Art
A discharge phenomenon that occurs between an electrostatically charged object and another object when they contact each other is called ESD (electrostatic discharge). An ESD to a semiconductor device may destroy the semiconductor device. The ESD can be typically modeled into three types: (a) HBM (Human Body Model) modeling discharge from a charged human body to a semiconductor device; (b) MM (Machine Model) modeling discharge from a charged apparatus to a semiconductor device; and (c) CDM (Charge Device Model) modeling discharge of electric charges on a semiconductor device to a grounded object.
FIG. 12 shows exemplary ESD surge current waveforms of CDM and HBM. In FIG. 12, the abscissa indicates time (nanosecond (ns)), and the ordinate indicates a current (ampere (A)). As shown in FIG. 12, in the HBM, charges held by an electrified human body are discharged through a resistance. Therefore, a current stress of about 1 A or so is generated for a relatively long time of about 100 ns. In the CDM, however, charges held by an electrified semiconductor are discharged to a grounded object without passing through a resistance. Therefore, a high current stress of about 10 A or so is applied within a very short time of about 1 ns.
As shown in FIG. 12, when the ESD occurs, a high current is applied to the semiconductor device in a short time. This may possibly cause “thermal breakdown”, blowing of an interconnection line or the like by Joule heating. Particularly, when an MIS (Metal Insulator Semiconductor) transistor structure, the mainstream of the recent LSI (Large Scale Integration) silicon (Si) devices, is used, the gate insulation film of the MIS transistor is likely to be dielectrically broken down when a high electric field is applied thereto due to the ESD. The destruction or breakdown of an element due to the ESD is a significant problem.
As an countermeasure against the ESD, various types of ESD protection circuits are generally formed between input/output (I/O) pins and an internal circuit. Here, the I/O pins are hereinafter referred to as input/output (I/O) pads since they are connected to pads on a silicon wafer in the wire bonding step. Such a protection circuit prevents a high voltage surge produced in the ESD phenomenon from being transmitted to the internal circuit, and thus prevents breakdown of a semiconductor element. Such a circuit for preventing a high voltage surge due to the ESD phenomenon from being transmitted to the internal circuit is generally called an ESD protection circuit.
For example, as described by Ker et al. in 1996 IEEE, IEDM96-889, pp. 889-892, a circuit in which a MOS Metal Oxide Semiconductor) transistor held in the OFF state in the normal operation mode is connected to an input/output (I/O) signal line is used as the ESD protection circuit. The normal operation mode herein indicates an operation mode in which a signal having an amplitude of a normal voltage level other than the ESD surge is transmitted.
FIG. 13 shows an example of the structure of a conventional ESD protection circuit. In FIG. 13, the ESD protection circuit includes a P-channel MOS transistor PT (hereinafter, a MIS transistor is described by a generally used MOS transistor) and an N-channel MOS transistor NT. The P-channel MOS transistor PT is connected between a signal transmission line 2 coupled to an I/O pad 1 and a power supply node, and the N-channel MOS transistor NT is connected between the signal transmission line 2 and a ground node.
The P-channel MOS transistor PT has its gate G, source S and back gate BG (N-well: substrate region) connected to the power supply node receiving an external power supply voltage VDD, and its drain D connected to the signal transmission line 2.
The N-channel MOS transistor NT has its gate G, back gate BG (P well: substrate region) and source S connected to the ground node, and its drain D connected to the signal transmission line 2. The signal transmission line 2 couples an internal circuit 3 and the I/O pad 1 to each other to transfer a signal between an outside of the device and the internal circuit 3.
In the normal operation mode, each of the MOS transistors PT and NT is non-conductive with its source S and gate G connected together, forming no current path. Therefore, the MOS transistors PT and NT will not exert an influence on an operation of the internal circuit 3.
As described below, when a ESD surge flows from the I/O pad 1 into the signal transmission line 2, parasitic bipolar transistor operation occurs in the MOS transistor PT or NT, to form a high-current flowing path from the drain D to the source S.
FIG. 14 exemplarily shows the cross-sectional structure of the N-channel MOS transistor NT shown in FIG. 13, and the parasitic bipolar transistor operation thereof. In FIG. 14, the N-channel MOS transistor NT includes a P-well 100 formed in, e.g., a silicon (Si) substrate region, N+ diffusion layers 102, 104 formed at the surface of the P-well 100 and spaced apart from each other, and a gate electrode 106 formed on the region of the P-well 100 between the N+ diffusion layers 102 and 104 with a not-shown gate insulation film interposed in between. The diffusion layers 102, 104 respectively serve as the drain D and the source S, and the P-well 100 serves as the back gate G.
In this N-channel MOS transistor NT, the gate electrode layer 106, the N+ diffusion layer 104 and the P-well 100 are coupled to the ground node. The N+ diffusion layer 102 is connected to the signal transmission line 2.
When a positive high voltage surge is generated, positive charges are supplied to the N+ diffusion layer 102. In response to this positive voltage surge, PN junction between the N+ diffusion layer 102 and the P-well 100 is reverse-biased, resulting in breakdown of the PN junction. As a result, a large current flows from the N+ diffusion layer 102 into the P-well 100. Due to the large current, there arises an impact current (impact ionization) phenomenon in the P-well 100, to generate a large number of electron-hole pairs. Of the electron-hole pairs thus generated, electrons (−) flow into the N+ diffusion layer 102 to which the positive voltage has been applied, whereas holes (+) flow into the ground node through the P-well 100. Assuming that the current produced when the holes flow through the P-well 100 is Ihole and the resistance value of the P-well 100 is Rsub, there is caused a voltage drop of Ihole·Rsub in the depth direction in the P-well 100. This voltage drop raises the potential of a shallow region 108 of the P-well 100 located just below the gate electrode layer 106 to a positive potential. As a result, in an NPN parasitic bipolar transistor formed of the drain N+ diffusion layer 102, the shallow P-well region 108 just below the gate, and the source N+ diffusion layer 104, the drain N+ diffusion layer 102 and the shallow P-well region 108 are reverse-biased, whereas the shallow P-well region 108 and the source N+ diffusion layer 104 are forward-biased. Therefore, this NPN parasitic bipolar transistor is turned ON. In other words, in the N-channel MOS transistor NT being in the OFF state with the gate G thereof grounded, the NPN parasitic bipolar transistor is turned ON in response to the ESD positive voltage surge applied to the drain N+ diffusion layer 102 through the signal transmission line 2. Through current amplifying operation of the NPN parasitic bipolar transistor, the MOS transistor NT can flow a large current from the drain N+ diffusion layer 102 into the ground node through the source N+ diffusion layer 104.
In the P-channel MOS transistor PT, the drain P+ diffusion layer and the back gate N-well are forward-biased in response to the positive voltage surge. Therefore, in the P-channel MOS transistor PT as well, a current due to positive voltage surge flows from the drain diffusion layer to the power supply node through the back gate. Thus, when the positive voltage surge is generated, the parasitic bipolar transistor operation of the N-channel MOS transistor NT and the diode operation resulting from forward-biasing of the PN junction diode of the P-channel MOS transistor PT drive a large current from the signal transmission line 2 to the ground node and the power supply node according to the surge voltage, to enable rapid absorption of the high voltage surge.
FIG. 15 exemplarily shows the cross-sectional structure of the P-channel MOS transistor PT in FIG. 13, and the parasitic bipolar transistor operation thereof upon generation of a negative voltage surge. In FIG. 15, the P-channel MOS transistor PT includes P+ diffusion layers 112, 114 formed at the surface of an N-well 110 and spaced apart from each other, and a gate electrode layer 116 formed on the region of the N-well 110 between the diffusion layers 112 and 114 with a not-shown gate insulation film interposed in between. The gate electrode layer 116, the P+ diffusion layer 114 and the N-well 110 are coupled to the power supply node and receive the power supply voltage VDD. The diffusion layers 112 and 114 respectively serve as the drain D and the source S, and the N-well 110 serves as the back gate. The P+ diffusion layer 112 is connected to the signal transmission line 2.
When a negative voltage surge is generated, PN junction between the drain P+ diffusion layer 112 and the N-well 110 is broken down, to cause an impact current for generating a large amount of electron-hole pairs in the N-well 110. Of the electron-hole pairs thus generated, electrons (−) flow into the power supply node through the N-well 110, whereas holes (+) flow into the drain P+ diffusion layer 112 held at a negative voltage level by the negative voltage surge. Assuming that the resistance of the N-well 110 is represented by Rsubn and the current produced by the electrons (−) is represented by Iele, there is caused a voltage rise of Iele·Rsubn along the depth direction in the N-well 110.
This voltage rise reduces the voltage level of a shallow N-well region 118 just below the gate electrode layer 116. Accordingly, the source P+ diffusion layer 114 and the shallow N-well region 118 are forward-biased, whereas the shallow N-well region 118 and the drain P+ diffusion layer 112 are reverse-biased. As a result, a PNP parasitic bipolar transistor formed of the source P+ diffusion layer 114, shallow N-well region 118, and drain P+ diffusion layer 112 is turned ON. A large current flows from the signal transmission line 2 into the power supply node, whereby the negative voltage surge is absorbed.
At this time, in the N-channel MOS transistor NT as well, the back gate P-well 100 and the drain N+ diffusion layer 102 are forward-biased. Responsively, due to the diode operation, a current flows from the back gate 100 into the drain N+ diffusion layer 102, whereby the negative voltage surge is absorbed.
Accordingly, the ESD protection circuit that uses the MOS transistors held in the OFF state in the normal operation mode as shown in FIG. 13 allows a large current to flow into the ground node and/or the power supply node upon generation of the ESD. Thus, a high current due to the surge can be prevented from flowing into the internal circuit 3, whereby the thermal breakdown and the dielectric breakdown of the gate insulation film can be prevented.
It is well known that, in order that the MOS transistors held in the OFF state in a normal operation provide an excellent ESD protection function, care should be taken of the MOS transistor layout.
FIG. 16 schematically shows the two-dimensional layout of conventional ESD protection MOS transistors. In FIG. 16, source regions SR, gate electrodes G and drain regions DR of the ESD protection MOS transistors are arranged alternately. The source region SR, the gate electrode G and the drain region DR each have a width W made large enough to drive a large current. The source region SR and the drain region DR electrically contact a signal line (signal transmission line or power supply/ground line) through a corresponding contact CT.
In this ESD protection MOS transistor, the contact CT and the gate electrode G must be separated from each other by an adequately large distance, d. According to the aforementioned article of Ker et al, the gate electrode G and the contact CT must be formed with a space d of 5 μm to 6 μm. This is because a drain electric field should be prevented from being increased due to a large surge current, for preventing breakdown of the gate insulation film by hot electrons.
Assuming that the contact CT has a diameter c, the source region SR and the drain region DR each interposed between the gate electrodes G have a width, (2d+c). Accordingly, the MOS transistor used as an ESD protection element must have a sufficiently large distance d between the gate electrode and the contact, and thus each of the source region SR and the drain region DR thereof must have a sufficiently large width Ws. According to the 0.2 μm design rule, the diameter, c, of the contact is generally about 0.2 μm or so. Accordingly, the width Ws of the source region SR and the drain region DR lies in the range from 10.2 to 12.2 μm according to the relation of (2·d+c).
In order to implement a sufficient ESD protection function, the MOS transistor must have a gate width Wg of at least 100 μm because it is required to drive a large current.
Accordingly, as shown in FIG. 17, the source region SR and the drain region DR each have an area of Wg·Ws. According to the 0.2 μm design rule, a source/drain diffusion layer generally has a parasitic capacitance of 1 fF/μm2 per unit area. Here, the parasitic capacitance of the source/drain diffusion layer indicates a depletion layer capacitance of PN junction between the drain/source diffusion layer and the well region. Accordingly, when the source region SR and the drain region DR as shown in FIG. 17 are utilized, the MOS transistor used for an ESD protection element has an extremely large parasitic capacitance of 1.02 pF to 1.22 pF formed between the source/drain diffusion layer and the well.
Such an extremely large parasitic capacitance between the well region and the diffusion region of the ESD protection element is not so fatal in a semiconductor memory and a logic circuit device operating at a relatively slow speed.
With recent widespread use of the mobile phones and actual implementation of the wireless LAN (Local Area Network) in practical uses, a high frequency semiconductor device capable of high frequency operation has been increasingly attracting attention, because the high frequency operation is essential to implement high performance and down-sizing and cost-down of electronic equipment used in the mobile phones and the wireless LAN. Conventionally, a III-V group compound semiconductor having high electron mobility such as GaAs is mainly used as a material for implementing the high frequency semiconductor device. However, recent rapid progress in miniaturization of a silicon (Si)-based MOS transistor enables fabrication of a MOS transistor having a fine gate length of 0.2 μm or less. A MOS transistor having such a fine gate length is significantly improved in transconductance Gm and high-frequency characteristics, to implement a MOS transistor having characteristics applicable to a high-frequency device operating in a giga-hertz (GHz) band. Accordingly, the large parasitic capacitance of the ESD protection element is a significant problem against a high frequency device using such a Si-MOS transistor (MOS transistor formed mainly from Si).
FIG. 18 schematically shows an equivalent circuit of the ESD protection element. With respect to the P-channel MOS transistor PT, a parasitic capacitance Cdp and a well resistance Rwn are connected in series between the signal transmission line 2 and the power supply node. With respect to the N-channel MOS transistor NT, a parasitic capacitance Cdn and a well resistance Rwp are connected in series between the signal transmission line 2 and the ground node.
The magnitude, |Z|, of the impedance Z of the capacitance C is generally represented as 1/(2·π·f·C), where f is a frequency. Accordingly, as the frequency f increases and a high frequency signal is to be processed, the magnitude, |Z|, of the impedance of the capacitance C is reduced. As the capacitance value C increases, the magnitude, |Z|, of the impedance Z of the capacitance C is further reduced. As shown in FIG. 18, when a high frequency signal HFSG is transmitted through the signal transmission line 2 to which the parasitic capacitances Cdp and Cdn of the drain diffusion layers are connected, the magnitude of the impedance of each of the parasitic capacitances Cdp and Cdn is significantly reduced.
As described in, e.g. 1999 IEEE BCTM 9.3, pp. 149-152, by Groves et al., a low resistance substrate (about 0.01 Ω-cm) is used in a silicon semiconductor device. This is because a material of a high quality is not available for a semi-insulating, high resistance substrate such as that used in a compound semiconductor device formed mainly from a compound semiconductor such as GaAs. Even when a well region is formed on the low resistance substrate, such well has a low resistance, resulting in low well resistances Rwn and Rwp. Accordingly, when the high frequency signal HFSG is transmitted to the signal transmission line 2, components of the high frequency signal HFSG flow through the ESD protection elements due to the small impedance between the signal transmission line 2 and the power supply node and the ground node, resulting in loss of the components of the high frequency signal HFSG through the well resistances Rwn and Rwp.
Thus, a high frequency circuit device that includes an ESD protection element formed of a MOS transistor held in the OFF state in the normal operation mode is large in signal loss, to hinder stable operation of a high frequency semiconductor device (internal circuit 3).
In other words, it is quite difficult to implement a reliable, high-performance, high frequency Si-MOS semiconductor device having high ESD immunity.
For ESD protection, it is conventionally attempt to additionally connect an ESD protection element such as a diode not only in such a silicon (Si)-based semiconductor circuit device but also in a high frequency semiconductor circuit device based on a compound semiconductor such as GaAs. However, in high frequency operation, a parasitic capacitance of the diode element is associated with the signal transmission line, to degrade high frequency characteristics of the semiconductor circuit device. Thus, a reliable high frequency compound semiconductor device having high ESD immunity has not been implemented (see, e.g., Bock et al., 1997 EOS/ESD Symposium, pp. 1-12).
A semiconductor device having low ESD immunity would cause breakdown due to an ESD surge in the step of inspecting and assembling a semiconductor chip after manufacturing the semiconductor device, resulting in a significantly reduced chip yield.
As described above, implementation of a reliable, high performance, high frequency semiconductor device having high ESD immunity is strongly desired not only in a Si-MOS high frequency device but also in a compound semiconductor high frequency element.